onbreak {resume}

transcript on
if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

# load designs
vlog -sv -work rtl_work DP_RAM0.v
vlog -sv -work rtl_work DP_RAM1.v
vlog -sv -work rtl_work Mul32.v
vlog -sv -work rtl_work SCalc.v
vlog -sv -work rtl_work tb_SCalc.v

# specify library for simulation
vsim -t 1ps -L altera_mf_ver -lib rtl_work tb_SCalc
# Clear previous simulation
restart -f

# activate waveform simulation
view wave

# add waves to waveform
add wave Clock_50
add wave Resetn 
add wave clrResult
add wave -unsigned uut/state
add wave -unsigned uut/count
add wave -unsigned uut/count_buf
add wave -unsigned DP0_Addr
add wave -unsigned DP1_Addr
add wave -signed DP0_Read 
add wave -signed DP1_Read
add wave -signed DP1_Write
add wave -signed uut/acc
add wave -unsigned uut/mulOp1
add wave -unsigned uut/mulOp2
add wave -unsigned uut/mulResult


# format signal names in waveform
configure wave -signalnamewidth 1

# run complete simulation
run -all


simstats
